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| FEDL9286-03 jul. 9, 2013 ml9286-xx vacuum fluorescent displ ay tube controller driver 1/37 general description the ml9286-xx is a 5 ?? 7 dot matrix type vacuum fluorescent display (vfd) tube controller driver ic which displays characters, numerics and symbols of a maximum of 20digits ? 1 line. dot matrix vfd tube drive signals are generated by serial data sent from a micro-controller. a display system is easily realized by internal rom and ram for character display. features ? logic power supply (v dd ) : 3.0v to 3.6v or 4.5v to 5.5v ? vfd tube drive power supply (v disp ) : 20v to 80v ? vfd driver output current (vfd driver output can be connected directly to the vfd tube. no pull-down resistor is required.) ? segment driver (seg1 to seg35) : ?5 ma (v disp = 80 v) ? segment driver (ad1 to ad2) : ?10 ma (v disp = 80 v) ? grid driver (com1 to com20) : ?30 ma (v disp = 80 v) ? content of display ? cgrom : 5 ? 7 dots 240 types (character data) ? cgram : 5 ? 7 dots 16 types (character data) ? adram : 24 (display timing) ? 2 bits (symbol data) ? dcram : 24 (display timing) ? 8 bits (register for character data display) ? display control function ? display digit : 9 to 20 digits ? gcram (grid control ram) : the display timing from t9 to t24 can be set. built-in multi grid function ? display duty (brightness adjustment) : 256 stages ? all lights on/off ? 4 interfaces with micro-controller : da, cs , cp , reset ? 1-byte instruction execution (excluding data write to ram and display duty set) ? built-in oscillation circuit ? crystal oscillation or ceramic oscillation ? package options al-pad chip (ml9286-xxwa) 80-pin plastic tqfp (p-tqfp80-1212-0.50) (ml9286-xxtb) 80-pin plastic qfp (p-qfp80-1414-0.65) (ml9286-xxga)
FEDL9286-03 ml9286-xx 2/37 block diagram v dd d-gnd r eset d a c p c s osc0 osc1 seg1 seg35 ad1 ad2 com1 com20 dcram 24w ? ? 35b adram 24w ? 2b 8-bit shift register command decoder control circuit timing generator 1 oscillator duty control grid driver ad driver segment driver write address counter address selector v disp 240w ? do gcram 24w ? 20b synco xout m /s read address counter synci l-gnd FEDL9286-03 ml9286-xx 3/37 pin configuration pad layout ch ip size : x : 3.79 mm ?? y : 3.89 mm chip thickness : 280 ? m pad size : 90 ? m ? 90 ? m(metal) 80 ? m ? 80 ? m(pv pad hole) x y 1 20 21 40 41 60 61 80 FEDL9286-03 ml9286-xx 4/37 pad coordinates pad no pad name x [ m] y [ m] pad no pad name x [ m] y [ m] 1 v disp 1760 -1347 41 com18 -1760 743 2 ad1 1760 -1237 42 com17 -1760 633 3 ad2 1760 -1127 43 com16 -1760 523 4 seg1 1760 -1017 44 com15 -1760 413 5 seg2 1760 -907 45 com14 -1760 303 6 seg3 1760 -797 46 com13 -1760 193 7 seg4 1760 -687 47 com12 -1760 83 8 seg5 1760 -577 48 com11 -1760 -27 9 seg6 1760 -467 49 com10 -1760 -137 10 seg7 1760 -357 50 com9 -1760 -247 11 seg8 1760 -247 51 com8 -1760 -357 12 seg9 1760 -137 52 com7 -1760 -467 13 seg10 1760 -27 53 com6 -1760 -577 14 seg11 1760 83 54 com5 -1760 -687 15 seg12 1760 193 55 com4 -1760 -797 16 seg13 1760 303 56 com3 -1760 -907 17 seg14 1760 413 57 com2 -1760 -1017 18 seg15 1760 523 58 com1 -1760 -1127 19 seg16 1760 633 59 v disp -1760 -1237 20 seg17 1760 743 60 v disp -1760 -1347 21 seg18 1063 1810 61 d-gnd -1553 -1810 22 seg19 953 1810 62 l-gnd -1381 -1810 23 seg20 843 1810 63 v dd -1211 -1810 24 seg21 733 1810 64 xout -1061 -1810 25 seg22 623 1810 65 synco -931 -1810 26 seg23 513 1810 66 cs -776 -1810 27 seg24 403 1810 67 da -602 -1810 28 seg25 293 1810 68 cp -428 -1810 29 seg26 183 1810 69 reset -254 -1810 30 seg27 73 1810 70 do -105 -1810 31 seg28 -37 1810 71 dmy-vdd 25 -1810 32 seg29 -147 1810 72 m /s 180 -1810 33 seg30 -257 1810 73 dmy-gnd 319 -1810 34 seg31 -367 1810 74 synci 464 -1810 35 seg32 -477 1810 75 osc0 641 -1810 36 seg33 -587 1810 76 osc1 886 -1810 37 seg34 -697 1810 77 v dd 1060 -1810 38 seg35 -807 1810 78 l-gnd 1230 -1810 39 com20 -943 1810 79 d-gnd 1402 -1810 40 com19 -1273 1810 80 v disp 1589 -1810 FEDL9286-03 ml9286-xx 5/37 pin configuration (top view) 80-pin plastic tqfp / qfp v disp d-gnd l-gnd v dd osc1 osc0 synci m /s dm y -v dd do dm y -gnd r eset da c s synco xout v dd l-gnd d-gnd 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v disp ad1 ad2 seg1 seg2 seg5 seg6 seg7 seg8 seg9 seg11 seg12 seg13 seg14 seg15 seg16 seg17 com1 v disp v disp com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 c p 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 seg4 seg3 seg10 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg32 seg33 seg34 seg35 com20 com19 seg31 FEDL9286-03 ml9286-xx 6/37 pin description pad no symbol type connects to description 4 38 seg1 to 35 o vfd tube anode electrode fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?5.0 ma 3958 com1 to 20 o vfd tube grid electrode fluorescent display tube grid electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?30.0 ma 2, 3 ad1, ad2 o vfd tube anode electrode fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube and a pull-down resistor is not necessary. i oh > ?10.0 ma 63,77 v dd ? power supply power supply pin for internal logic. 1, 59, 60,80 v disp ? power supply power supply pin for driving fluorescent tubes. 61, 79 d-gnd ? power supply d-gnd pin for driver circuits of a vfd tube. connect this pin to the external l-gnd. 62, 78 l-gnd ? power supply l-gnd pin for logic circuits. connect this pin to the external d-gnd. 67 da i micro controller serial data input. (built-in schmitt circuit) input from lsb. (positive logic) 68 cp i micro controller shift clock input. (built-in schmitt circuit) serial data is shifted on the rising edge of cp . 66 cs i micro controller chip select input. (built-in schmitt circuit) serial data transfer is disabled when cs pin is "h" level. 69 reset i micro controller reset input. (built-in schmitt circuit)"low" initializes all the functions. for initial status see reset function. 75 osc0 i 76 osc1 o crystal or ceramic resonator pins for self-oscillation. connect these pins to the crystal and capacitors or to the ceramic resonator and capacitors. the target oscillation frequency is 4.0 mhz. ( note that the device includes the feed back resistor. see application circuit. ) 70 do o ? serial data output pin for test mode. (positive logic) do not use in normal operation. ( do outputs ?l? level in normal operation. ) 64 xout o cascade connection generate output 1/4 clock for osc0. the main usage is to connect this pin to the osc0 pin of the adjacent ic when the ml9286 is cascaded. 65 synco o cascade connection frame sync signal output pin. a synchronous pulse is output from this pin immediately before the start of the frame. 74 synci i cascade connection frame sync signal input pin. a synchronous pulse is input from this pin immediately before the start of the frame. 72 m /s ? cascade connection this pin is used for setting the master or salve. when m /s = low, the ml9286 is master mode. when m /s = high, the ml9286 is slave mode. 73 dmy-gnd o ? the output pin to fix the adjacent input pin to the gnd level. use this pin only for this purpose. 71 dmy-v dd o ? the output pin to fix the adjacent input pin to the v dd level. use this pin only for this purpose. FEDL9286-03 ml9286-xx 7/37 absolute maximum ratings gnd = 0 v parameter symbol condition rating unit supply voltage (1) v dd ? ?0.3 to +6.5 v supply voltage (2) v disp ? ?0.3 to +85 v input voltage v in ? ?0.3 to v dd +0.3 v operating temperature tj ? ?40 to +125 c i o1 com1 to com20 ?40.0 to 2.0 i o2 ad1, ad2 ?20.0 to 2.0 i o3 seg1 to seg35 ?10.0 to 2.0 output current i o4 do ?2.0 to 2.0 ma power dissipation p d ta ?? 25?c 80-pin plastic tqfp / qfp 400 mw storage temperature t stg ? ?55 to +150 c recommended operating conditions gnd = 0 v parameter symbol condition min. typ. max. unit 3.3v unit power supply used 3.0 3.3 3.6 v supply voltage (1) v dd 5.0v unit power supply used 4.5 5.0 5.5 v supply voltage (2) v disp ? 20 ? 80 v cp frequency f c ? ? ? 2.0 mhz oscillation frequency f osc self-oscillation 3.5 4.0 4.5 mhz frame frequency f fr digit = 1 to 20, self-oscillation 171 195 220 hz t j al-pad chip ?40 ? +125 c operating temperature ta 80-pin plastic tqfp / qfp ?40 ? +105 c FEDL9286-03 ml9286-xx 8/37 electrical characteristics dc characteristics (v dd = 3.0 to 3.6v or 4.5 to 5.5v, v disp = 20 to 80 v, ta = ?40 to +105c) parameter symbol applied pin condition min. typ. max. unit v dd = 3.0 to 3.6 v 0.8 v dd ? ? high level input voltage v ih *1 v dd = 4.5 to 5.5 v 0.7 v dd ? ? v v dd = 3.0 to 3.6 v ? ? 0.2 v dd low level input voltage v il *1 v dd = 4.5 to 5.5 v ? ? 0.3 v dd v high level input current i ih *1 v in = v dd ?2.0 ? +2.0 ? a low level input current i il *1 v in = 0 v ?2.0 ? +2.0 ? a v oh1 com1 to 20 v disp = 80 v, i oh1 = ?30 ma v disp ?4.0 ? ? v v oh2 ad1, ad2 v disp = 80 v, i oh2 = ?10 ma v disp ?4.0 ? ? v v oh3 seg1 to 35 v disp = 80 v, l oh3 = ?5 ma v disp ?4.0 ? ? v high level output voltage v oh4 do,xout, synco i oh4 = ?400 ? a v dd ?0.3 ? ? v v ol1 *2 v disp = 80 v,i ol1 = 1 ma ? ? 1.0 v low level output voltage v ol2 do,xout, synco i ol2 = 400 ? a ? ? 0.3 v v dd ? ? 3 i dd1 v disp v dd = 3.6v,f osc = 4.0mhz, no load, duty=240/256, digit =1 to 20, all lights on mode ? ? 2 ma v dd ? ? 3 i dd2 v disp v dd = 3.6v,f osc = 4.0mhz, no load, duty=0/256, digit =1 to 9, all lights off mode ? ? 1 ma v dd ? ? 4 i dd3 v disp v dd = 5.5v,f osc = 4.0mhz, no load, duty=240/256, digit =1 to 20, all lights on mode ? ? 2 ma v dd ? ? 4 current consumption (1) i dd4 v disp v dd = 5.5v,f osc = 4.0mhz, no load, duty=0/256, digit =1 to9, all lights off mode ? ? 1 ma i dds v dd ? ? 20 ? a current consumption (2) i disps v disp no clock supply. ta=85c tj=85c ? ? 20 ? a? *1) cs , cp , da, reset ,synci *2) com1 to 20, seg1 to 35, ad1, ad2 FEDL9286-03 ml9286-xx 9/37 ac characteristics (v dd = 3.0 to 3.6v or 4.5 to 5.5v, v disp = 20 to 80 v, ta = ?40 to +105c) parameter symbol condition min. max. unit cp frequency f c ? ? 2.0 mhz cp pulse width t cw ? 200 ? ns da setup time t ds ? 200 ? ns da hold time t dh ? 200 ? ns cs setup time t css ? 250 ? ns cs hold time t csh self-oscillation 16 ? ? s cs wait time t csw ? 350 ? ns data processing time t doff self-oscillation 8 ? ? s reset pulse width t wres when reset signal is input from microcontroller, etc. externally 350 ? ns reset time t rson ? t oscon ? ns da wait time t rsoff ? 250 ? ns t r t r = 20% to 80% ? 2.0 ? s all output slew rate t f c i = 100 pf t f = 80% to 20% ? 2.0 ? s oscillation start-up time t oscon ? * 1 *1 t oscon depends on the type of crystal or resonator. refer to characteristic data of crystal or resonator used. FEDL9286-03 ml9286-xx 10/37 timing diagram symbol v dd = 3.0 to 3.6v v dd = 4.5v to 5.5v v ih 0.8 v dd 0.7 v dd v il 0.2 v dd 0.3 v dd data timing reset timing output timing all driver outputs t f t r 0.8v disp 0.2v disp c s c p da t css t ds t dh t doff valid v ih v il 1/f c t cw t csh t csw v il v ih v il v ih t cw valid valid valid 0.8 v dd v ih 0.0 v v il v ih v il v dd r eset da t wres t rsoff t rson FEDL9286-03 ml9286-xx 11/37 digit output timing (for t24 timing set, at a duty of 240/256) digit output timing (for t20 timing set, at a duty of 240/256) com1 com2 com3 com4 com5 com6 gnd frame cycle t 1 = 6144t (t 1 = 6.144ms when f osc = 4.0 mhz) v disp t=4/ f osc gnd v disp com19 com20 ad1-2 seg1-35 display timing t 2 = 240t (t 2 = 240 ? ? com2 com3 com4 com5 com6 frame cycle t 1 = 5120 t (t 1 = 5.12ms when f osc = 4.0 mhz) t=4/ f osc com19 com20 ad1-2 seg1-35 display timing t 2 = 240 t (t 2 = 240 ? s when f osc = 4.0 mhz) blank timing t 3 = 16 t (t 3 = 16 ? s when f osc = 4.0 mhz) gnd v disp gnd v disp FEDL9286-03 ml9286-xx 12/37 functional description commands list lsb 1st byte msb lsb 2nd byte msb no command b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 1 dcram data write x0 x1 x2 x3 x4 1 0 0 c0 c1 c2 c3 c4 c5 c6 c7 c0 c5 c10 c15 c20 c25 c30 * c1 c6 c11 c16 c21 c26 c31 * c2 c7 c12 c17 c22 c27 c32 * c3 c8 c13 c18 c23 c28 c33 * 2 cgram data write x0 x1 x2 x3 * 010 c4 c9 c14 c19 c24 c29 c34 * 3 adram data write x0 x1 x2 x3 x4 1 1 0 c0 c1 * * * * * * c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 4 gcram data write * * * * * 001 c16 c17 c18 c19 * * * * 5 display duty set * * * * * 1 0 1 d0 d1 d2 d3 d4 d5 d6 d7 6 number of timing set k0 k1 k2 k3 * 011 7 all lights on/off l h * * * 111 8 test mode t0 t1 t2 t3 1 000 note 1: when data is written to ram (dcram, cgram, adram) contin uously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. note 2: the test mode is used for inspection before shipment. it is not a user function. * : don't care xn : address specification for each ram cn : character code specification for each ram dn : display duty specification kn : number of display timing specification h : all lights on instruction l : all lights off instruction tn : test mode specification FEDL9286-03 ml9286-xx 13/37 positional relationship between segn and adn (one digit) a dram written data. corresponds to 2nd byte cgram written data. corresponds to 2nd byte cgram written data. corresponds to 3rd byte cgram written data. corresponds to 4th byte cgram written data. corresponds to 6th byte cgram written data. corresponds to 5th byte c0 a d1 c0 seg1 c5 seg6 c10 seg11 c15 seg16 c20 seg21 c25 seg26 c30 seg31 c1 seg2 c6 seg7 c11 seg12 c16 seg17 c21 seg22 c26 seg27 c31 seg32 c2 seg3 c7 seg8 c12 seg13 c17 seg18 c22 seg23 c27 seg28 c32 seg33 c3 seg4 c8 seg9 c13 seg14 c18 seg19 c23 seg24 c28 seg29 c33 seg34 c4 seg5 c9 seg10 c14 seg15 c19 seg20 c24 seg25 c29 seg30 c34 seg35 c1 a d2 FEDL9286-03 ml9286-xx 14/37 data transfer method and command write method display control command and data are written by an 8-bit serial transfer. write timing is shown in the figure below. setting the cs pin to "low" level enables a data transfer. data is 8 bits and is sequentially input into the da pin from lsb (lsb first). as shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the cp pin. if 8-bit data is input, internal load signals are automatically generated and data is written to each register and ram. therefore it is not necessary to input load signals from the outside. setting the cs pin to "high" disables data transfer. data input from the point when the cs pin changes from "high" to "low" is recognized in 8-bit units. * when data is written to ram (dcram, adram, cgram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. reset function r es et is executed when the reset pin is set to "l", (when turning power on, for example) and initializes all functions. initial status is as follows: ? address of each ram ....................................... address "00"h ? data of each ram ............................................. all contents are undefined ? display timing ................................................... t1 to t24 ? brightness ad justment........................................ 0/256 ? all display lights on or off ............................ off mode ? segment output .................................................. all segment outputs (seg1 to seg35) go "low" ? common output ................................................. all common outputs (com1 to com20) go "low" ? ad output .......................................................... all ad outputs (ad1 and ad2) go "low" please set the functions again according to "setting flowchart" after reset. t doff b0 lsb c s c p b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 msb 1st byte lsb msb 2nd byte command and address data t csh b0 b1 b2 b3 b4 b5 b6 b7 lsb msb 2nd byte character code data of the next address character code data when data is written to dcram* da t doff FEDL9286-03 ml9286-xx 15/37 description of commands and functions 1. dcram data write (s pecifies the addresses 00h to 1fh of dcram an d writes the character codes of cgrom and cgram.) dcram (data control ram) has a 5-bit address to store the character codes of cgrom and cgram. the character code specified by dcram is converted to a 5 ? 7 dot matrix character pattern via cgrom or cgram. (the dcram can store 24 timing.) [command format] to specify the character code of cgrom and cgram continuously to the next address, specify only character codes as follows. the addresses of dcram are automatically incremented. specification of an address is unnecessary. after the character code setting up to 24 timing is comp leted, to set a character code from dcram address 00h continuously, set a dummy character code to dcram addresses between 18h and 1fh. (dcram address is incremented automatically up to 1fh and after return to 00h) x0 x1 x2 x3 x4 1 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : selects dcram data write mode and specifies dcram address (ex: specifies dcram address 00h.) : specifies the character codes of cgrom and cgram (written into dcram address 00h) c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : specifies the character codes of cgrom and cgram (written into dcram address 01h) : specifies the character codes of cgrom and cgram (written into dcram address 02h) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (25th) lsb msb : specifies the character codes of cgrom and cgram (written into dcram address 17h) c0 c1 c2 c3 c4 c5 c6 c7 FEDL9286-03 ml9286-xx 16/37 x0 (lsb) to x4 (msb): dcram addresses (5 bits: 24 timing) c0 (lsb) to c7 (msb): character codes of cgrom and cgram (8 bits: 256 characters) [timing setting positions and set dcram addresses] hex x0 x1 x2 x3 x4 timing setting hex x0 x1 x2 x3 x4 timing setting 00 0 0 0 0 0 t1 10 0 0 0 0 1 t17 01 1 0 0 0 0 t2 11 1 0 0 0 1 t18 02 0 1 0 0 0 t3 12 0 1 0 0 1 t19 03 1 1 0 0 0 t4 13 1 1 0 0 1 t20 04 0 0 1 0 0 t5 14 0 0 1 0 1 t21 05 1 0 1 0 0 t6 15 1 0 1 0 1 t22 06 0 1 1 0 0 t7 16 0 1 1 0 1 t23 07 1 1 1 0 0 t8 17 1 1 1 0 1 t24 08 0 0 0 1 0 t9 18 0 0 0 1 1 ? 09 1 0 0 1 0 t10 19 1 0 0 1 1 ? 0a 0 1 0 1 0 t11 1a 0 1 0 1 1 ? 0b 1 1 0 1 0 t12 1b 1 1 0 1 1 ? 0c 0 0 1 1 0 t13 1c 0 0 1 1 1 ? 0d 1 0 1 1 0 t14 1d 1 0 1 1 1 ? 0e 0 1 1 1 0 t15 1e 0 1 1 1 1 ? 0f 1 1 1 1 0 t16 1f 1 1 1 1 1 ? c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (26th) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (33rd) lsb msb : specifies the character codes of dummy cgrom and cgram (not written into dcram address) : specifies the character codes of dummy cgrom and cgram (not written into dcram address) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (34th) lsb msb : specifies the character codes of cgrom and cgram (dcram address 00h is rewritten) c0 c1 c2 c3 c4 c5 c6 c7 FEDL9286-03 ml9286-xx 17/37 2. cgram data write (specifies the addresses of cgram and writes character pattern data.) cgram (character generator ram) has a 4-bit address to store 5 ? 7 dot matrix character patterns. a character pattern stored in cgram can be displayed by specifying the character code (address) by dcram. the address of cgram is assigned to 00h to 0fh. (all the other addresses are the cgrom addresses.) (the cgram can store 16 types of character patterns.) [command format] to specify character pattern data continuously to the next address, specify only character pattern data as follows. the addresses of cgram are automatically incremented. specification of an address is therefore unnecessary. the 2nd to 6th byte (character pattern data) are regarded as one data item, so 200 ns is sufficient for t doff time between bytes. c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specifies 1st column data (written into cgram address 00h) c1 c6 c11 c16 c21 c26 c31 * b0 b1 b2 b3 b4 b5 b6 b7 3rd byte (3rd) lsb msb : specifies 2nd column data (written into cgram address 00h) x0 x1 x2 x3 * 0 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects cgram data write mode and specifies cgram address. (ex: specifies cgram address 00h.) c2 c7 c12 c17 c22 c27 c32 * b0 b1 b2 b3 b4 b5 b6 b7 4th byte (4th) lsb msb : specifies 3rd column data (written into cgram address 00h) c3 c8 c13 c18 c23 c28 c33 * b0 b1 b2 b3 b4 b5 b6 b7 5th byte (5th) lsb msb : specifies 4th column data (written into cgram address 00h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (6th) lsb msb : specifies 5th column data (written into cgram address 00h) FEDL9286-03 ml9286-xx 18/37 x0 (lsb) to x3 (msb) : cgram addresses (4 bits: 16 characters) c0 (lsb) to c34 (msb) : character pattern data (35 bits: 35 outputs per digit) * : don't care c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (7th) lsb msb : specifies 1st column data (written into cgram address 01h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (11th) lsb msb : specifies 5th column data (written into cgram address 01h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (12th) lsb msb : specifies 1st column data (written into cgram address 02h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (16th) lsb msb : specifies 5th column data (written into cgram address 02h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (77th) lsb msb : specifies 1st column data (written into cgram address 0fh) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (81st) lsb msb : specifies 5th column data (written into cgram address 0fh) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (82nd) lsb msb : specifies 1st column data (cgram address 00h is written) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (86th) lsb msb : specifies 5th column data (cgram address 00h is written) FEDL9286-03 ml9286-xx 19/37 [cgrom addresses and set cgram addresses] refer to romcode table hex x0 x1 x2 x3 cgrom address hex x0 x1 x2 x3 cgrom address 00 0 0 0 0 ram00(00000000b) 08 0 0 0 1 ram08(00001000b) 01 1 0 0 0 ram01(00000001b) 09 1 0 0 1 ram09(00001001b) 02 0 1 0 0 ram02(00000010b) 0a 0 1 0 1 ram0a(00001010b) 03 1 1 0 0 ram03(00000011b) 0b 1 1 0 1 ram0b(00001011b) 04 0 0 1 0 ram04(00000100b) 0c 0 0 1 1 ram0c(00001100b) 05 1 0 1 0 ram05(00000101b) 0d 1 0 1 1 ram0d(00001101b) 06 0 1 1 0 ram06(00000110b) 0e 0 1 1 1 ram0e(00001110b) 07 1 1 1 0 ram07(00000111b) 0f 1 1 1 1 ram0f(00001111b) positional relationship between the output area of cgrom and that of cgram note: cgrom (character generator rom) has an 8-bit address to generate 5 u 7 dot matrix character patterns. cgram can store 240 types of character patterns. c0 c5 c10 c15 c20 c25 c30 c1 c6 c11 c16 c21 c26 c31 c2 c7 c12 c17 c22 c27 c32 c3 c8 c13 c18 c23 c28 c33 c4 c9 c14 c19 c24 c29 c34 area that corresponds to 2nd byte (1st column) area that corresponds to 3rd byte (2nd column) area that corresponds to 5th byte (4th column) area that corresponds to 6th byte (5th column) area that corresponds to 4th byte (3rd column) FEDL9286-03 ml9286-xx 20/37 3. adram data write (s pecifies the addresses 00h to 1fh of adram and writes symbol data.) adram (additional data ram) has a 5-bit address to store symbol data. symbol data specified by adram is directly output without cgrom and cgram. (the adram can store 2 types of symbol patterns for each digit.) the terminal to which the contents of adram are output can be used as a cursor. [command format] to specify symbol data continuously to the next address, specify only symbol data as follows. the address of adram is automatically incremented. specification of addresses is therefore unnecessary. after the symbol data setting up to 24 timing is completed, to set a symbol data from adram address 00h continuously, set a dummy symbol data to adram addresses between 18h and 1fh. (adram address is incremented automatically up to 1fh and after return to 00h) c0 c1 * ** * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : sets symbol data (written into adram address 00h.) x0 x1 x2 x3 x4 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects adram data write mode and specifies adram address (ex: specifies adram address 00h.) c0 c1 * ** * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb : sets symbol data (written into adram address 01h) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : sets symbol data (written into adram address 02h) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (25th) lsb msb : sets symbol data (written into adram address 17h) FEDL9286-03 ml9286-xx 21/37 x0 (lsb) to x4 (msb) : adram addresses (5 bits: 24 characters) c0 (lsb) to c1 (msb) : symbol data (2 bits: 2-symbol data per digit) * : don't care [timing setting and adram addresses] hex x0 x1 x2 x3 x4 timing setting hex x0 x1 x2 x3 x4 timing setting 00 0 0 0 0 0 t1 10 0 0 0 0 1 t17 01 1 0 0 0 0 t2 11 1 0 0 0 1 t18 02 0 1 0 0 0 t3 12 0 1 0 0 1 t19 03 1 1 0 0 0 t4 13 1 1 0 0 1 t20 04 0 0 1 0 0 t5 14 0 0 1 0 1 t21 05 1 0 1 0 0 t6 15 1 0 1 0 1 t22 06 0 1 1 0 0 t7 16 0 1 1 0 1 t23 07 1 1 1 0 0 t8 17 1 1 1 0 1 t24 08 0 0 0 1 0 t9 18 0 0 0 1 1 ? 09 1 0 0 1 0 t10 19 1 0 0 1 1 ? 0a 0 1 0 1 0 t11 1a 0 1 0 1 1 ? 0b 1 1 0 1 0 t12 1b 1 1 0 1 1 ? 0c 0 0 1 1 0 t13 1c 0 0 1 1 1 ? 0d 1 0 1 1 0 t14 1d 1 0 1 1 1 ? 0e 0 1 1 1 0 t15 1e 0 1 1 1 1 ? 0f 1 1 1 1 0 t16 1f 1 1 1 1 1 ? c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (26th) lsb msb : sets dummy symbol data (not written into adram address) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (33rd) lsb msb : sets dummy symbol data (not written into adram address) c0 c1 * * * * * * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (34th) lsb msb : sets dummy symbol data (adram address 00h is rewritten) FEDL9286-03 ml9286-xx 22/37 4. gcram data write (multi grid function) (writes data by the number of com outputs for digits) gcram (grid control ram) has a 24-bit address to control the number of com outputs for digits. gcram outputs specified data directly to comn, allowing com outputs to be controlled arbitrarily. it is also possible to supply a large current by connecting a plurality of coms outside the ml9286. for example, when com19 and com20 are connected, the ml9286 has 19 display digits. in this case, the user specifies ?19? as the number of display digits. write grid data at gcram addresses 00h and later. carry out this mode before putting-out-lights mode release. refer to a setting operation flow chart about the details of a setup. write com data"0" in the gcram address which is not used for incorrect display prevention. moreover, this setting can set com of three a timing or less. when four or more setting, any com is not set. (the com outputs are all ?l?) [command format] lsb msb b0 b1 b2 b3 b4 b5 b6 b7 1st byte * * * * * 0 0 1 : selects a gcram data write mode. (1st) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 2nd byte c0 c1 c2 c3 c4 c5 c6 c7 : specifies com data. (2nd) (written into gcram address 00h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 3rd byte c8 c9 c10 c11 c12 c13 c14 c15 : specifies com data. (3rd) (written into gcram address 00h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 4th byte c16 c17 c18 c19 * * * * : specifies com data. (4th) (written into gcram address 00h) c0 (lsb) to c19 (msb): grid control data (20 bits) *: don?t care note: to specify additional grid control data, specify the grid control data as shown below. the gcram addresses are automatically incremented. the second byte to the fourth byte (for grid data) are treated as a single piece of element and the byte-byte t doff can be 200 ns. FEDL9286-03 ml9286-xx 23/37 lsb msb b0 b1 b2 b3 b4 b5 b6 b7 2nd byte c0 c1 c2 c3 c4 c5 c6 c7 : specifies com data. (5th) (written into gcram address 01h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 4th byte c16 c17 c18 c19 * * * * : specifies com data. (7th) (written into gcram address 01h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 2nd byte c0 c1 c2 c3 c4 c5 c6 c7 : specifies com data. (71st) (written into gcram address 17h) lsb msb b0 b1 b2 b3 b4 b5 b6 b7 4th byte c16 c17 c18 c19 * * * * : specifies com data. (73rd) (written into gcram address 17h) with the above operations, com data of up to 24 digits are set. to set other com data at gcram addresses 00h and later, specify dummy symbol data at gcram addresses 18h to 1fh (to automatically increment the gcram address and set the gcram address to 00h). [gcram addresses (digit positions) and com positions] gcram address (hex) t1 (00) t2 (01) t3 (02) t22 (15) t23 (16) t24 (17) com1 c0 c0 c0 c0 c0 c0 com2 c1 c1 c1 c1 c1 c1 com3 c2 c2 c2 c2 c2 c2 com4 c3 c3 c3 c3 c3 c3 com5 c4 c4 c4 c4 c4 c4 com16 c15 c15 c15 c15 c15 c15 com17 c16 c16 c16 c16 c16 c16 com18 c17 c17 c17 c17 c17 c17 com19 c18 c18 c18 c18 c18 c18 com20 c19 c19 c19 ? ? ? ? ? c19 c19 c19 FEDL9286-03 ml9286-xx 24/37 [gcram output example] 1. when 20-digit display of multi grid. FEDL9286-03 ml9286-xx 25/37 2. when 8-digit display of multi grid. FEDL9286-03 ml9286-xx 26/37 5. display duty set (writes a display duty value to the duty cycle register.) display duty adjusts brightness in 256 stages (0/256 to 240/256) using 8-bit data. when the reset signal is input, the duty cycle register value is "0". (see "reset function") always execute this instruction before turning the display on, then set a desired duty value. [command format] d0 (lsb) to d7 (msb) : display duty data (8 bits: 0/256 to 240/256 stages) * : don't care [relation between setup data and controlled com/ad/seg duty] hex d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 com/ad/seg duty 00 0 0 0 0 0 0 0 0 0 0 0/256 01 1 0 0 0 0 0 0 0 0 0 1/256 02 0 1 0 0 0 0 0 0 0 0 2/256 ef 1 1 1 1 1 1 0 1 1 1 239/256 f0 0 0 0 0 0 0 1 1 1 1 240/256 fe 0 1 1 1 1 1 1 1 1 1 240/256 ff 1 1 1 1 1 1 1 1 1 1 240/256 ? the state when reset signal is input. * * * * * 1 0 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects display duty set. d0 d1 d2 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : sets duty value set. d3 d4 d5 d6 d7 FEDL9286-03 ml9286-xx 27/37 6. number of timing set (writes the number of display timing to the display timing register.) the number of timing set can t9 to t24 display timing using 4-bit data. when the reset signal is input, the number of timing register value is "0". (see ?reset function?) always execute this instruction to change the number of timings before turning the display on. [command format] k0 (lsb) to k3 (msb) : number of timing data (4 bits) * : don't care [relation between setup data and timing set] hex k0 k1 k2 k3 timing setting hex k0 k1 k2 k3 timing setting 0 0 0 0 0 t1 to t24 8 0001 t1 to t16 1 1 0 0 0 t1 to t9 9 1001 t1 to t17 2 0 1 0 0 t1 to t10 a 0101 t1 to t18 3 1 1 0 0 t1 to t11 b 1101 t1 to t19 4 0 0 1 0 t1 to t12 c 0011 t1 to t20 5 1 0 1 0 t1 to t13 d 1011 t1 to t21 6 0 1 1 0 t1 to t14 e 0111 t1 to t22 7 1 1 1 0 t1 to t15 f 1111 t1 to t23 * the state when reset signal is input. k0 k1 k2 k3 * 0 1 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects the number of timing set mode FEDL9286-03 ml9286-xx 28/37 7. all display lights on/off set (turns all display lights on or off.) when the reset signal is input, all display lights off mode is set. (see ?reset function?) all display lights on mode is used primarily for display testing. all display lights off mode is primarily used for display blink and to prevent malfunction when power is turned on. [command format] [set data and display state of seg and ad] l h display state of seg and ad 0 0 normal display 1 0 sets all outputs to low 0 1 sets all outputs to high 1 1 sets all outputs to high (the state when reset signal is input.) l h * * * 1 1 1 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects all display lights on or off mode and specifies display operation l and h: display operation data * : don't care FEDL9286-03 ml9286-xx 29/37 setting flowchart (power applying included) apply v disp a ll display lights off number of timing set display duty setting cgram data write mode (with address setting) cgram character code cgram is character code a nother ram to be set? releases all display lights off mode a dram data write mode (with address setting) a dram character code a dram is character code dcram data write mode (with address setting) dcram character code dcram is character code select a ram to be used status of all outputs by r es e t signal input display operation mode no no no yes yes yes yes end apply v dd no address is automatically incremented address is automatically incremented address is automatically incremented write ended? write ended? write ended? gcram data write mode gcram code gcram is character code no yes write ended? address is automatically incremented FEDL9286-03 ml9286-xx 30/37 power-off flowchart display operation mode turn off v dd turn off v disp FEDL9286-03 ml9286-xx 31/37 caution for power-on sequence set v dd and v disp as the same voltage and connect them at the outside of ic. to prevent the mulfunction, turn on the driver power supply v disp after the logic power supply v dd is turned on at power-on sequence. and also, turn off the driver power supply v disp before the logic power supply v dd is turned off at power-off sequence. [voltage] [time] v dd terminal voltage v disp terminal voltage >2.0 sec >2.0 sec FEDL9286-03 ml9286-xx 32/37 application circuit notes: *1. the application circuit indicates a circuit by which fluorescent display tube filaments are ac driven using a heater transformer. contact fluorescent display tube manufacturers for the methods and circuits of driving fluorescent display tube filaments. *2. keep the wires between the osc0 pin and the crystal or ceramic resonator as short as possible to avoid generating noise. *3 for oscillation capacitor values, refer to data of the crystal or ceramic resonator used. ml9286 -xx micro- controller 20 35 2 r eset v dd com1-20 seg1-35 ad1-2 v dd gnd gnd v disp osc0 osc1 da c p c s output port r 3 v dd v disp zd 5 ? 7-dot matrix fluorescent display tube grid (digit) anode (segment) anode (segment) heater transformer gnd gnd crystal or ceramic resonator *1 *1 *1 *2 *3 gnd FEDL9286-03 ml9286-xx 33/37 application circuit (cascade connection) notes: *1. please set the display timing register of master ic and slave ic to the same value. open open open open open open open gnd vfd 20 characters 2 line osc0 osc1 synci dmy-gnd cs da cp reset do dmy-gnd m /s synco xout 35 35 20 osc0 osc1 synci dmy-gnd cs da cp reset do dmy-gnd m /s synco dmy-v dd xout seg seg com com open ml9286 master ml9286 slave x?tal FEDL9286-03 ml9286-xx 34/37 reference data graphs illustrating the v disp versus driver output current capability relationship are shown below. care must be taken not to use the total power in excess of allowable power dissipation. v disp voltage vs output current of each driver 0 10 20 30 20 40 60 80 v disp voltage [v] output current [ma] com1 to com20 (condition:v oh = v disp -4.0v) ad1 to ad2 (condition:v oh = v disp -4.0v) seg1 to seg35 (condition:v oh = v disp -4.0v) FEDL9286-03 ml9286-xx 35/37 ml9286-01 rom code *rom code is the character set for seg1 to seg35. 00000000b(00h) to 00001111b(0fh) are the cgram addresses msb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 111 1 lsb 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ram0 ram1 ram2 ram3 ram4 ram5 ram6 ram7 ram8 ram9 rama ramb ramc ramd rame ramf FEDL9286-03 ml9286-xx 36/37 revision history page document no. date previous edition current edition description fedl9286-01 mar. 1, 2010 ? ? final edition 1 1 1 add qfp package fedl9286-02 jan. 25, 2013 37 ? delete package dimensions 5, 7 5, 7 add qfp package FEDL9286-03 jul. 9, 2013 36 ? delete rom code 02 FEDL9286-03 ml9286-xx 37/37 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-a utomation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the pr escribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd. |
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